The present invention relates to a process for forming, on a single wafer, p- and n- channel MOS transistors along with vertical, isolated NPN and PNP transistors.
Currently CMOS is the dominant IC technology. It combines a high density of transistors with low power dissipation and high yield (due to its low sensitivity to semiconductor crystal defects.) Bipolar transistors, on the other hand, are faster with larger current drive, but consume more power and have lower VLSI yield. Integration of isolated vertical NPN transistors into a CMOS process results in faster bipolar performance. By retaining the majority of the transistors in CMOS, the low power and high yield of a CMOS process are maintained.
In analog circuits, isolated NPN transistors increase the bandwidth of Opamps five-fold compared to pure CMOS implementation. They also help in easier realization of bandgap voltage references. The addition of isolated, vertical PNP transistors to the NPN's constitutes the Complementary BiCMOS process. The bandwidths of Opamps is now increased by an additional factor of at least two. Circuit noise and settling time are less. Bias generators are easily realized. It also achieves rail-to-rail analog output with low distortion combined with capability to source or sink high currents.
It is more difficult to integrate isolated vertical PNP transistors into a CMOS process (non-isolated PNP transistors are connected to the P substrate or a P epitaxial layer and are more easily implemented).
The formation of a vertical PNP transistor and a CMOS process without using a buried P+ layer is suggested by Sullivan in U.S. Pat. No. 4,507,847. However, Sullivan does not provide details on how this could be accomplished.
A structure which can provide non-isolated vertical PNP transistors in a CMOS process is discussed in Y. Okada, et al., "An Advanced Bipolar-MOS-i.sup.2 l Technology With a Thin Epitaxial Layer for Analog-Digital VLSI", IEEE Transactions on Electron Devices, Vol. Ed.-32, No. 2, February 1985, pp. 232-236.
The following is a list of Complementary Bipolar Processes with isolated Vertical PNP's:
I. P. C. Davis, J. F. Graczyk and W. A. Griffin, "High Slew Rate Monolithic Operational Amplifier Using Compatible Complementary PNP's", IEEE J. Solid-State Circuits, Vol. SC-14, Vol.2, February 1979.
II. T. Kekkawa, T. Suganuma, K. Tanaka and T. Hara, "A New Complementary Transistor Structure for Analog Integrated Circuits", Int'l Solid State Circuits Conf. Tech Digest, 1980 p. 65-68.
III. D. Monttcelli, J. Wright, B. Small and B. Geczy, "200 MHz PNP Transistors Spawn Fast Analog Chips", Electronic Design, August 1986, p. 111-116.
IV. "First ADI CB Process Part is High Speed 12-Bit DAC Electronic Engineering Times". Monday, Sept. 7, 1987.
The vertical PNP transistors in the above references are formed through a buried P+ collector which is created by a P+ implant before the growing of an N epitaxial layer.
A BiCMOS process with lateral NPN and PNP transistors is shown in U.S. Pat. No. 4,050,965.
A number of references disclose the formation of vertial NPN transistors only, with no PNP transistors, such as U.S. Pat. Nos. 4,547,791; 4,536,945; 4,346,512; 4,016,596; and 4,299,024.